1. Field of the Invention:
This invention relates to non-volatile semiconductor memory devices and more particularly to integration techniques for combining variable threshold non-volatile devices with fixed threshold support devices within a single semiconductor substrate.
2. The Prior Art:
Variable threshold non-volatile semiconducting memory elements are well known in the art. These devices basically comprise an MOSFET element including a gate structure comprising a thin tunneling dielectric layer, usually silicon dioxide and a thicker dielectric trapping layer, which may be silicon nitride (MNOS) or aluminum oxide (MAOS). The application of a field in excess of a critical level across the dielectric layers causes charge to be stored at the dielectric interface provided that a source of carriers is also provided. An opposite polarity field causes charge to be removed from the interface. Charge trapped at the interface will remain for extended periods of time without the application of external fields or potentials and is commonly designated as non-volatile storage, as contrasted with dynamic storage found in other conventional semiconductor storage circuits which require either the presence of DC supply potentials or charge refresh circuitry.
Although MNOS and MAOS field effect transistors provide date storage within a single device structure, and therefore extremely high packing density, the time required to charge, or write, data states is considerably longer than that required for dynamic storage circuits. As a result, MNOS and MAOS devices have been proposed for use in memories requiring infrequent writing, that is Read Mostly Memories (RMM). Little potential has been previously predicted for use of non-volatile memory devices in Random Access Memories (RAM), in view of the slow write times required.
The design and fabrication of MNOS variable threshold devices is considerably more complex than that required for fixed threshold conventional MOSFET devices. The article, "Optimization of Charge Storage in the MNOS Memory Device", by A. M. Goodwin et al, RCA Review, June 1970, pp. 342-354, describes a typical design approach for the variable threshold gate dielectric of an MNOS device to provide an optimum charge storage capacity and charge retention time. A p-channel device is described having an oxide thickness of 20 angstroms and a nitride layer formed by the ammonization of silane at a temperature of 700.degree.C.
In order to provide critical fields necessary to write and erase charge in non-volatile devices, drive voltages in excess of those normally encountered in MOSFET circuits are required. Considerable attention has previously been given to developing the dielectric structure in nondevice areas over which these high voltages must pass in order to prevent parasitic devices. U.S. Pat. No. 3,803,705, to Goodwin describes field dielectric structures including multiple layers of thermal silicon dioxide and silicon nitride (the same materials used in the variable threshold gate dielectric) covered by a thick layer of pyrolitic silicon dioxide. U.S. Pat. No. 3,646,527 to Wada et al describes n-channel variable threshold devices having an alumina or silicon nitride gate dielectric and a field dielectric of alumina, silicon dioxide/alumina, silicon nitride/alumina or silicon nitride. The article, "Triple-Density MNOS Memory Array with Field Shield", by P. J. Krick, IBM Technical Disclosure Bulletin, November 1973, pp. 1723-5, describes the use of a polysilicon field shield to prevent parasitic devices in an MNOS memory array circuit.
An additional problem presented by non-volatile device fabrication, is that of integrating both variable threshold memory devices and fixed threshold devices on the same semiconductor substrate to provide a functional integrated memory. The last mentioned article and U.S. Pat. No. 3,733,591 to Cricchi teach the use of p-n junction isolation between array and support areas of a substrate. In the former, both variable threshold and fixed threshold devices utilize MNOS gate dielectric structure. In the latter, more conventional silicon dioxide gate dielectric is used.
Commonly assigned, copending application Ser. No. 411,857 of Potter entitled, "Isolated Fixed and Variable Threshold Field Effect Transistor Fabrication Technique", which describes an MAOS integration technique in which the gate dielectric for the variable threshold devices is formed as initial steps in the fabrication process.
Although a substantial quantity of prior art exists which relates to variable threshold devices useful in memory systems, no effort has considered specific structures and fabrication methods which provide compatible solutions to all of the problems presented in the development of an actual product. This is particularly true with respect to n-channel devices, which although favored in MOSFET applications in view of performance superiority, particularly speed, over p-channel devices. The inherent problems of providing all enhancement mode n-channel variable threshold MNOS devices of suitable consistency and reliability for use in a product has, prior to the subsequent invention, eluded those skilled in the art.